In many modern electronics applications, it is desirable to convert a digital value to an analog signal. For example, digital-to-analog converters (DACs) are commonly used in the feedback path of analog-to-digital converters (ADCs). In some ADCs, sigma-delta modulation (or alternatively, delta-sigma modulation) is used to reduce the effect of quantization error and improve signal-to-noise ratio (SNR).
Some ADCs utilize continuous-time sigma-delta modulators, that is, sigma-delta modulators constructed using continuous-time circuitry. Continuous-time sigma-delta modulators can be clocked at higher sampling frequencies which improves the performance of the sigma-delta ADC.
In practice, however, a high-speed sigma-delta ADC can be limited in performance by the DACs in the feedback path. For example, some sigma-delta ADCs utilize a DAC in the feedback path that uses a return-to-zero (RZ) pulse scheme. Other sigma-delta ADCs utilize a DAC in the feedback path that uses a non-return-to-zero (NRZ) pulse scheme.
In general, a DAC using an RZ pulse scheme can provide better immunity to inter-symbol interference compared to a DAC using a NRZ pulse scheme. However, a DAC using an RZ pulse scheme is more susceptible to the effects of clock jitter than DAC using a NRZ pulse scheme. Furthermore, a DAC using an RZ pulse scheme can have increased slew rate requirements compared to a DAC using a NRZ pulse scheme. For these reasons there continues to be a need for DACs that can be used in ADCs while providing relatively good immunity to clock jitter, inter-symbol interference, and while having reduced slew rate requirements.